A Novel Architecture Implementation Of Fir Filter Using Truncated Multiplier
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated
multipliers. We consider both the optimization of bit width and hardware resources without enduring the frequency response
and output signal precision. To reduce total area cost Non-uniform coefficient quantization with proper filter order is
proposed. Multiple constant multiplication/accumulation in a direct FIR structure is implemented by means of an enhanced
version of truncated multipliers. Comparisons with earlier FIR design approaches show that the proposed designs achieve the
best area and power results.