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Paper Title :
Implementation Of 64-Bit Decimal Matrix Code For Correcting Cell Upsets In Static Random Access Memories

Author :Chamundeswari K, R Kalyan, V Keerthy Rai

Article Citation :Chamundeswari K ,R Kalyan ,V Keerthy Rai , (2014 ) " Implementation Of 64-Bit Decimal Matrix Code For Correcting Cell Upsets In Static Random Access Memories " , International Journal of Advances in Science, Engineering and Technology(IJASEAT) , pp. 121-126, Volume-2,Issue-3

Abstract : In this paper, novel per-word 64- bit DMC was proposed to assure the reliability of memory. Here to detect and correct maximum 32 errors. The proposed protection code utilized decimal algorithm to detect errors, so that more errors were detected and corrected. The obtained results showed that the proposed scheme has a superior protection level against large MCUs in memory. Besides, the proposed decimal error detection technique is an attractive opinion to detect MCUs in CAM because it can be combined with BICS to provide an adequate level of immunity. Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder.

Type : Research paper

Published : Volume-2,Issue-3


DOIONLINE NO - IJASEAT-IRAJ-DOIONLINE-1166   View Here

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