Paper Title
Performance Enhancement Of Double Gate Junctionless Transistor Using High-K Spacer

In this paper the impact of varying spacer dielectric on both sides of gate oxide on the device performance of a symmetric double gate Junctionless transistor (DGJNT) is reported. The performance parameter of the device considered in this study are ION/IOFF, DIBL and subthreshold slope. It is observed that there is a significant improvement in ION/IOFF, DIBL and subthreshold slope with spacer dielectric.