Paper Title
Efficient Routability-Aware Transistor Placement Considering Various Folding Styles for Advanced Technology Nodes

Transistor placement is the key step to dominate the quality of standard cell layouts because of the limited routing resource of cell layouts. A routability-aware transistor placement algorithm can then help generate high-quality transistor placements favoring cell routing to reduce potential rule violation and layout quality as well. In this paper we propose aroutability- aware dynamic programming (DP)–based transistor placement algorithm that can efficiently generate transistor placements favoring cell routing and considering diffusion shape constraints. Then, a LEGO-liked assembling method considers the issue of different folding styles to generate transistor placements of high-driving cells. Our results show that the proposed methods can have dramatic routability and runtime improvement compared to existing works. Indexterms - Standard cell, Transistor placement, Dynamic programming (DP), LEGO.