Design And Analysis Of Low Power Sts Pulse Triggered Flip-Flop Using 250nm CMOS Technology
In this paper, a comparison of existing Flip-Flop (FF) system with different parameters is reported. A New design
of Flip-Flop has been proposed, having a structure of explicit pulse-triggered with a modified true single phase clock latch
based on signal feed through scheme. The post-layout simulation results using CMOS 250nm technology affirms that in the
proposed system delay is reduced when compared with existing systems. This Flip-Flop has a shorten delay which leads to
improve in speed and power saving too. Explicit Pulse-triggered Flip-Flop(FF), pulse signal can be shared to other Flip-Flop.
In the Proposed FF scheme not only the delay but also the power delay product, a true metric for comparison is optimized.