Paper Title
Implementation Of Decimal Matrix Code For Correcting Cell Upsets In Static Random Access Memories

Now a days to maintain good level of reliability, it is necessary to protect memory cells using protection codes, for this purpose, various error detection and correction methods are being used. In this paper 64-bit Decimal Matrix Code was proposed to assure the reliability of memory. Here to detect and correct up to 32 errors. The proposed protection code utilized decimal procedure to detect errors, so that more errors were detected and corrected. The results showed that the proposed scheme has a protection level against large MCUs in memory. Besides, the proposed decimal error detection technique is astriking opinion to detect MCUs in CAM since it can be combined with BICS to provide an adequate level of immunity. Transient multiple cell upsets (MCUs) are suitable major problems in the reliability of memories exposed to radiation environment. In the proposed method we are implement 64-bit decimal matrix for error correction in memories. In the proposed module to increase the error correction rate compared to the 32-bit decimal matrix code. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes include been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not enhanced in all cases. Moreover, the ERT (encoder-reuse technique) is proposed to reduce the area overhead of extra circuits exclusive of disturbing the total encoding and decoding processes. ERT use DMC encoder itself to be part of the decoder.