Paper Title
An Efficient FPGA Implementation of 64-Bit Compressor based Vedic Multiplier

A design of high speed Vedic Multiplier based on the compressor which takes advantage of old Indian Vedic mathematics that has improved performance is defined in this paper. Almost each advanced design today needs low power, high speed, small area multipliers in system. In this compressor based architecture, parameters like hardware speed, complexity, power and delay are improved over conventional multiplier. The system of ancient Indian Vedic mathematics, is based on unique technique of solutions based on only 16 sutras. 4:2 compressors and 7:2 compressors are being used for improvement that boost the speed of multiplier and reduces the area required than conventionally used multiplier. 5:2 compressors and two full adders are used to construct 7:2 compressors. The design proposed in this paper was implemented on FPGA to obtain the speed and area improvements, over the reference designs. Keywords - Vedic, Sutras, FPGA, HDL.