Low Power FGMOS Current-Mode Multiplier Circuits With Applications In Analog Signal Processing
The current mode analog multiplier circuit using floating gate MOS (FGMOS) transistors operating in saturation
region is presented. Since FGMOS stores charge for long period of time, the presented structure have the advantage of low
supply voltage and low power consumption. The squaring characteristics of MOS transistor improve frequency response and
the bandwidth of a multiplier. The proposed structure is designed for implementing in 180-nm CMOS technology in cadence
virtuoso environment. The circuit’s power consumption and supply voltage is about 47.26 µw and 1v respectively.
Keywords- Current-Mode Operation, Floating Gate Mos, Multiplier, Translinear Loop.