Paper Title
Hardware Implementation of AES for Image Encryption: AES-CTR and AES-MECB

We present in this paper the hardware implementation of two image encryption architectures based on the Advanced Encryption Standard (AES). The basis being a previous implementation of the main AES block that was done on the Xilinx Artix 7 Basys 3 XC7A35T-1CPG236C FPGA after completing the design flow in Xilinx Vivado Design Suite 2018.2. The block cipher architecture has modified into two stream cipher architectures to suitably readapt it into an image encryption schemes: AES-CTR, and AES-MECB, the latter being a modification of the AES-ECB proposed by us. The image encryption schemes had their efficiency tested and the essential parameters where extracted. Xilinx Vivado Design Suite 2018.2 has been used for the circuit design flow using Verilog HDL, and MATLAB R2018a has been used for extracting the binary data to be used from the image as well as to repack the data stream obtained from our circuits into the image matrix. Keywords - FPGA, Verilog HDL, AES, ECB, CTR, Image Encryption.