Securing Data Transmission with Efficient Hardware Implementation of the AES`
We present in this paper an optimized hardware implementation of the Advanced Encryption Standard (AES). The overall optimization of this algorithm was achieved through a deep study and careful logic optimization at various architectural levels, and also keeping in mind design trade-offs. By making use of the tower field in the SBox and using direct computation in some other blocks of the circuit, we arrived at a topology having balanced hardware parameters, and can be used as a basis to develop more complex AES based encryption systems. A low area utilization was achieved and the power utilization was 323mW for a throughput of 506Mbps. The implementation was done on the Xilinx Artix 7 Basys 3 XC7A35T-1CPG236C FPGA after completing the design flow in Xilinx Vivado Design Suite 2018.2. Keywords - FPGA, Verilog HDL, Advance Encryption Standard (AES).