Efficient NoC Router Method in VLSI using Packet Switching Method
A New Network-On-Chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed
NoC is based on new error detection mechanisms suitable for dynamic NoC, where the number and position of processor
elements or faulty blocks vary during runtime. The design is compatible with high speed to be used in Xilinx FPGA-based
system. The ability to provide multiple display resolutions and a customizable internal FIFO make the proposed architecture
suitable for several FPGA devices.
In the existing method, adaptive routing algorithm errors mechanisms are able to distinguish permanent and transient errors
and localize accurately the position of the faulty blocks data bus, input port, output port in the NoC routers, while preserving
the throughput, the network load, and the data packet latency.
In the Proposed router, Packet Switching method is introduced. We provide localization capacity analysis of the presented
mechanisms, NoC performance evaluations, and field-programmable gate array synthesis. The proposed router will consume
less delay and area than the existing router.
Address based routing algorithm provides header value to the packet and fixed the header value also assign remaining values
as data. The header values are fixed with the help of packet valid. During the transmission which path have to select assign
that port only enable and remaining two ports are disable. When change the header value just changes the packet valid value
then automatically the next bit will be assigned data values. Each packet contains address information that identifies the
sending computer and intended recipient. Using these address, network switches and routers determinant how best to transfer
the packet between hops on the path to its destination.
Keywords - NOC, FPGA, Packet Switching, Routing Algorithm, Packet Format.