Paper Title
Performance Improvement Of A Modified Carry Select Adder

This paper contains various performance improvement techniques of a modified architecture of carry select adder. The conventional Carry Select Adder is first designed and then modification is done to improve performance parameters such as delay reduction, power dissipation, power Delay Product. We simulated these designs along with a modified design in cadence VIRTUOSO environment in 180nm CMOS technology and compared their performance parameters are compared. Keywords – CMOS Logic, Carry Select Adder, GDI Approach, High Performance