Improved Analytical Modeling For Junctionless Transistor
In this paper, we have derived and proposed an analytical model of junctionless transistor by solving poisson
equation with variable separation method. The 2-D poisson equation in both silicon and oxide regions are solved to deduce
expressions of surface potential, threshold voltage and drain induced barrier lowering of double gate junctionless transistor.
Behavior of Derived expression is compare with analytical model of junctionless DG-MOSFET and TCAD sentaurus
results. Proposed results give good agreement with these results.
Index Terms- Junctionless transistor, 2-D poisson equation, surface potential, Short channel effect (SCE), Drain Induced
Barrier Lowering (DIBL).