Paper Title
Area Efficient 4-Bit Successive Approximation Register ADC

This paper presents the implementation of a 4 bit Successive approximation Analog to Digital converter. The SAR ADC designed operates at a frequency of 4.167MHz. It uses 4 flip flop for the implementation of 4 bit SAR ADC. In normal SAR ADC separate registers are required for storing of the initial bit values and for storing the results of the comparison. The architecture is implemented in 55nm. It facilitates a non redundant register as a result of which the area can be reduced. An SNDR of 22.3 dB and SNR of 24.2 dB is achieved. Index Terms—Analog To Digital Converter, Area Efficient, Successive Approximation Register.