Design of high performance wallace tree multiplier using compressors and parellel prefix adders
Wallace tree multipliers are considered as one of the high speed and efficient multipliers. This paper proposes an architecture for a Wallace tree multiplier that comprises of a 3:2, 4:2, 5:2 compressors, half adder and a parallel prefix adder, resulting in reduction of delay to a significant extent, while simultaneously restraining a large increase in the area of the design. The architecture presented in this paper can be used for high speed Wallace tree multiplier of any size on any suitable hardware. The proposed design gives 41% reduction in the delay as compared to the conventional ripple carry adder based Wallace tree multiplier.
Keywords: Wallace Tree Multiplier, Compressors, Ladner-Fischer, Carry Save Adders, Ripple Carry Adders.