Paper Title
Design of Pulse Triggered Transmission Gate Based Power Efficient Flip Flop

In this paper, a transmission gate based low power pulse triggered flip-flop design is conferred. In this configuration, the clock pulse is generated with two input AND gate circuitry for reducing the discharging path and reduce the circuit complexity. In the proposed design input to output driving path inverter is deleted and the feedback is removed along with pseudo NMOS and the transistor is substituted with transmission gate logic. The transmission gate driven by generated clock pulse is utilized to drive the flip flop output. As compared to the conventional pulse triggered flip-flop, the proposed pulse triggered flip-flop design features are best power, along with minimum number of transistors. This is designed and simulated in X-manager 4 with 3.5 V supply voltage and 350 Nanometer technology. Index terms- Transmission Gate, Power Delay Product.