An FPGA Implementation Of Ieee - 754 Double Precision Floating Point Unit Using Verilog
Abstract- Arithmetic circuits form an important class of circuits in digital systems. With the remarkable progress in the very
large scale integration (VLSI) circuit technology, many complex circuits, unthinkable yesterday have become easily
realizable today. Algorithms that seemed impossible to implement now have attractive implementation possibilities for the
future. In this paper an arithmetic unit based on IEEE standard for floating point numbers has been implemented on FPGA
Board. Here FPU follows IEEE double precision format. The arithmetic unit implemented has a 64-bit processing unit which
allows various arithmetic operations such as, Addition, Subtraction, Multiplication and Division on floating point numbers.
Each operation can be selected by a particular operation code. We see that the overhead for double precision is less than that
for single precision. The unit comprises of rounding and exception unit as specified in format. The FPU design achieved the
operating frequency of 107MHz.