A Novel CNTFET Based Power and Delay Optimized Hybrid Full Adder
In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology
is presented. Two input full swing XOR gate is design using 4 transistors and then, this is used to generate Sum and Carry
output signals. Sum and carry signals are generated by using Gate-Diffusion-Input (GDI) which reduces the number of
transistors involved. Proposed design simulated with different voltages (0.8V, 0.9V, 1V) and results are better design as
compared to existing circuits in terms of Power, Delay and Power-Delay-Product (PDP). For different operating voltages
PDP are 8.6045zJ, 2.004zJ and 4.74aJ respectively for the proposed design.
Keywords - Carbon Nanotube Field-Effect Transistor (CNTFET); Nanotechnology; Full Adder; Low Power; High Speed;
Power Delay Product.