International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 113
Paper Published : 1559
No. of Authors : 4245
  Journal Paper


Paper Title :
Delay Optimization of Concatenation and Incrementation Carry Skip Adder

Author :K. Lakshmi Tejaswi, K.Babulu

Article Citation :K. Lakshmi Tejaswi ,K.Babulu , (2017 ) " Delay Optimization of Concatenation and Incrementation Carry Skip Adder " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 29-31, Volume-5,Issue-11

Abstract : The architecture of a 32-bit Carry Skip Adder to achieve less area, less power consumption, less delay is presented in this paper. Totally two architectures are explained in this paper. In Conv-CSKA, 2:1 MUXs are used in the skip logic in between the RCA stages to skip the carry. This 2:1 MUX requires 12 transistors to implement in CMOS level which occupies large amount of area which in turn increases the power consumption. So, in CI-CSKA these 2:1 MUX are replaced with AOI,OAI logic to implement the skip logic technique and they require only 6 transistors to implement. So, area, power, delay are reduced to 50% when compared with Conv-CSKA. In addition, in case of CI-CSKA, except for the first stage, all the inputs for the RCAs are zero hence the name concatenation. So, there is no need for all the RCAs to wait for the input carry. Finally the comparison results reveal that there is 50%decrement in the power consumption, area and delay of the proposed structure when compared with the Conv-CSKA. Index Terms - 32-bit Carry Skip Adder ,less delay ,2:1 MUX, AOI, OAI logic ,CI-CSKA.

Type : Research paper

Published : Volume-5,Issue-11


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-10176   View Here

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