International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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May. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 111
Paper Published : 1546
No. of Authors : 4203
  Journal Paper


Paper Title :
FPGA Implementation Of Phase Locked Loop (PLL) With Synchronous Reset

Author :Tanvir Zaman Khan, Prajoy Podder, Mamdudul Haque Khan, M. Muktadir Rahman

Article Citation :Tanvir Zaman Khan ,Prajoy Podder ,Mamdudul Haque Khan ,M. Muktadir Rahman , (2014 ) " FPGA Implementation Of Phase Locked Loop (PLL) With Synchronous Reset " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 1-4, Volume-2,Issue-8

Abstract : Modern high frequency, high performance system-on-chip design is heading to include more and more analog or mixed signal circuits as well as digital blocks. As the complexity of a system grows, it becomes more and more important to implement the system simulation and top-down design methodology as well. In this paper, we have designed a phase locked loop using Verilog and Xilinx .Considering the rapid growth in computer automation and computer networking sector, FPGA implementation technique of PLL has been adopted in this paper. Verilog is a hardware description language (HDL) used to model electronic systems. This PLL model basically used for synchronization of closed loop RF control signals. In ASIC system sometimes it is very important to synchronize the input signal with the output signal. Synchronous PLL can be used for this purpose. This paper has considered the minimum number of devices like Flip Flop, comparator, adder or subtractor due to enhance the efficiency of the system and the time delay of PLL is also considered to be much less.

Type : Research paper

Published : Volume-2,Issue-8


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