Paper Title :Performance Enhancement Of Double Gate Junctionless Transistor Using High-K Spacer

Author :Anup Kumar Mandia, Ashwani K. Rana

Article Citation :Anup Kumar Mandia ,Ashwani K. Rana , (2014 ) " Performance Enhancement Of Double Gate Junctionless Transistor Using High-K Spacer " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 5-8, Volume-2,Issue-8

Abstract : In this paper the impact of varying spacer dielectric on both sides of gate oxide on the device performance of a symmetric double gate Junctionless transistor (DGJNT) is reported. The performance parameter of the device considered in this study are ION/IOFF, DIBL and subthreshold slope. It is observed that there is a significant improvement in ION/IOFF, DIBL and subthreshold slope with spacer dielectric.

Type : Research paper

Published : Volume-2,Issue-8

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