Paper Title :Design of Viterbi Decoders with Reduced Power Consumption

Author :Kamal Kalita, Ashutosh Sharma

Article Citation :Kamal Kalita ,Ashutosh Sharma , (2018 ) " Design of Viterbi Decoders with Reduced Power Consumption " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 48-52, Volume-6,Issue-2

Abstract : Viterbi decoding is the best technique for decoding the convolutional codes. It has been widely deployed in many wireless communication systems to improve the capacity of the communication channels. Viterbi decoders used in digital wireless communications are complex and dissipate large amount of power. Now a days most of the portable and hand held devices are powered by battery devices. So for these kinds of devices, the power dissipation along with speed and area are three major concern of VLSI design. It is known that dynamic power dissipation is about 90% to 95% of overall power dissipation in a CMOS circuit. Many techniques have been proposed to reduce dynamic power dissipation. These techniques can be applied at different levels of digital design, such as the algorithmic level, the architectural level, the gate level and the circuit level. In this paper, we have considered pruning threshold and use of multiplexer to reduce power dissipation. Though various platforms can be used for realizing a Viterbi Decoder, Field Programmable Gate Arrays (FPGAs) has been used as it gives the designer flexibility for a programmable solution, the performance of a custom solution and lowering overall cost. The FPGA also adds design flexibility and adaptability with optimal device utilization conserving both boards space and system power.. Keywords - Convolutional Code, Viterbi algorithm, Low power.

Type : Research paper

Published : Volume-6,Issue-2

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