International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 89
Paper Published : 1423
No. of Authors : 3841
  Journal Paper

Paper Title
On Chip Generation Of Functional Tests For High Transition Faults Using Fixed Hardware

Abstract
In this proposed method we are test the one combinational circuit. Here this combinational circuit having 36-bit input and 7-bit output. ISCAS-85 C432 27-channel interrupt controller is a combinational benchmark circuit. This paper described an on-chip test generation method for functional broadside tests. The hardware was based on the application of primary input sequences initial from a known reachable state, thus using the circuit to produce additional reachable states. Random primary input sequences were changed to avoid repeated synchronization and thus yield varied sets of reachable states. The hardware structure was simple and fixed, and it was tailored to a given circuit only through the following parameters: the length of the LFSR used for producing a random primary input sequence; the length of the primary input sequence; the specific gates used for modifying the random primary input sequence; the particular gate used for selecting applied tests; and the seeds for the LFSR. With the proposed on-chip test generation method, the circuit is used for generate reachable states for the duration of test application. This alleviates the want to compute reachable states offline.


Author - K. B.Meena Kumari, V.Thrimurthulu, N.P.Dharani

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| Published on 2014-09-30
   
   
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