Paper Title :Fault Tolerance Improvement of The Secured Circuits

Author :Ghania Ait Abdelmalek, Rezki Ziani, Rabah Mokdad

Article Citation :Ghania Ait Abdelmalek ,Rezki Ziani ,Rabah Mokdad , (2018 ) " Fault Tolerance Improvement of The Secured Circuits " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 50-52, Volume-6,Issue-9

Abstract : One of the major problems in testing a system-on-chip is dealing with the optimal choice of the test sequence. In this paper, we propose an efficient test sequence for TMR secure circuits. The test sequence is a high level method based on three pulsations. An extension to the sequence with one pulsation is proposed and by simulation results its effectiveness in achieving a higher fault tolerance interval is demonstrated.

Type : Research paper

Published : Volume-6,Issue-9

	|		PDF	|	Viewed - 67	|	Published on 2018-12-11