International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Apr. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 133
Paper Published : 1712
No. of Authors : 4737
  Journal Paper


Paper Title :
Implementation Of CDF 5/3 Wavelet Transform

Author :Shriram Hegde, S Ramachandran

Article Citation :Shriram Hegde ,S Ramachandran , (2014 ) " Implementation Of CDF 5/3 Wavelet Transform " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 36-38, Volume-2,Issue-11

Abstract : The Discrete wavelet transform (DWT) has become one of the most used techniques for signal analysis and image processing applications.. In this paper, we propose FPGA implementation of CDF 5/3 wavelet transform. The lifting scheme 5/3 algorithm is used for implementing 1D-DWT architecture. The 2D-DWT lifting based architecture is designed using 1D-DWT lifting architectures. The proposed architecture uses less hardware interns of dedicated multipliers compared to existing architectures. The proposed architecture is implemented on Virtex-IV FPGA and it is observed that the parameters such as LUT’s and delays are efficient.

Type : Research paper

Published : Volume-2,Issue-11


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