International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
.
Follow Us On :
current issue
Volume-11,Issue-11  ( Nov, 2023 )
ARCHIVES
  1. Volume-11,Issue-10  ( Oct, 2023 )
  2. Volume-11,Issue-9  ( Sep, 2023 )
  3. Volume-11,Issue-8  ( Aug, 2023 )

Statistics report
Feb. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 131
Paper Published : 1705
No. of Authors : 4719
  Journal Paper


Paper Title :
An Efficient FPGA Implementation of 128-Bit Advanced Encryption Standard Algorithm

Author :Kishor Raosaheb Chavan

Article Citation :Kishor Raosaheb Chavan , (2019 ) " An Efficient FPGA Implementation of 128-Bit Advanced Encryption Standard Algorithm " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 28-30, Volume-7,Issue-3

Abstract : Security is the most important factor in storing and exchange of the digital data/information, hence encryption of data at the source and decryption of data at destination is of prime importance for digital data processing system and any data communication networks in this rapidly increasing world of internet today. Cryptography hold a major and prime role in providing security to digital data. As per the recommendations of the National Institute of Standards and Technology (NIST) [3], Advanced Encryption Standard (AES) is a standard based on secret key encryption. The AES is used to achieve se-cure data communication and which is based on design principle of SP-network. According to AES standard, inputs to AES encryption or decryption are 128 bits of plain-text and a key either of 128, 192 or 256 bits. When 128 bit plain-text block is processed by same function number of times using derived and different key for each round where each key is obtained processing original input key, 128 bits of encrypted output cipher block is obtained. The AES algorithm describes use of Exclusive-ORing operation, S-Box substitution, shifting of Rows, Mixing of columns and adding of round key for each iteration. All the text blocks such as Plain-text block, encrypted cipher-text block and in-process or intermediate state text block can be mapped or considered in 4 cross 4 matrix form. The proposed approach in this paper presents FPGA based implementation of 128 bits AES Cryptography (Encryption and Decryption) system using speed efficient parallel substitution since it minimizes the execution time in the SubByte transform which boosts max frequency by double. The design & verification methodology to be employed is Verilog HDL in Xilinx/ Intel (Altera) tools and FPGA. Keywords - AES, NIST, FPGA, HDL, High Throughput, Pipelining, SBox, MixColumn.

Type : Research paper

Published : Volume-7,Issue-3


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-15145   View Here

Copyright: © Institute of Research and Journals

| PDF |
Viewed - 70
| Published on 2019-06-03
   
   
IRAJ Other Journals
IJEEDC updates
Volume-11,Issue-10(Oct ,2023) Want to join us ? CLick here http://ijeedc.iraj.in/join_editorial_board.php
The Conference World

JOURNAL SUPPORTED BY

ADDRESS

Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740