International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Apr. 2021
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 97
Paper Published : 1483
No. of Authors : 4016
  Journal Paper


Paper Title :
Design Of Low Power R-2r DAC For High- Speed Communications

Author :K.Naga Kanya, V.S.V.Prabhakar

Article Citation :K.Naga Kanya ,V.S.V.Prabhakar , (2014 ) " Design Of Low Power R-2r DAC For High- Speed Communications " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 10-14, Volume-2,Issue-12

Abstract : Digital-to-Analog Converter (DAC) is a device used to convert the input signal that is in digital form into an output signal in the analog form (voltage). The resulting DAC output voltage is proportional with the digital value applied to the DAC. In this paper, an analysis of 6-bit R-2R DAC is proposed. The DAC is aimed at low power dissipation, using 6-bit resolution. The DAC is used for high speed applications. The update rate for this DAC is 5GS/s. The key components used are Operational amplifier (op-amp), Binary switch and R-2R Ladder. The CMOS schematics are designed and simulated using Mentor Graphics Tool with technology TSMC 0.18um. Measurements of Integral (INL) and Differential (DNL) non linearity of the DAC design results are INL=±0.41 LSB and DNL=±0.25 LSB. Keywords: R-2R ladder, OP-AMP, Switches, INL, DNL, MOSFET

Type : Research paper

Published : Volume-2,Issue-12


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