International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
.
Follow Us On :
current issue
Volume-10,Issue-5  ( May, 2022 )
ARCHIVES
  1. Volume-10,Issue-4  ( Apr, 2022 )
  2. Volume-10,Issue-3  ( Mar, 2022 )
  3. Volume-10,Issue-2  ( Feb, 2022 )

Statistics report
Aug. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 113
Paper Published : 1559
No. of Authors : 4245
  Journal Paper


Paper Title :
Design And Implementation Of Stereo Sound Enhancement On FPGA

Author :Shreedeep Gangopadhyay, Rumpa Biswas, Moumita Acharya

Article Citation :Shreedeep Gangopadhyay ,Rumpa Biswas ,Moumita Acharya , (2013 ) " Design And Implementation Of Stereo Sound Enhancement On FPGA " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 83-89, Volume-1,Issue-3

Abstract : In digital media, quality of stereo sound is more enjoyable than mono sound and most of the audio appliances in the market are using stereo quality transmission The prime objective of this paper is to focus on the principle concepts of stereo sound enhancement techniques and implement a stereo sound enhancement algorithm on modern FPGA board. Field programmable gate arrays (FPGAs), provide one of the major alternative in hardware platform scenario due to its reconfiguration nature, low price and marketing speed and it provides us a custom hardware platform where we can design and develop the desired algorithm and architecture using different built-in custom logic, DSP cores and automatic HDL code generation facility. The algorithm we have implemented is based on the concept of taking spatial information in audio components and enhanced it using delay and adding-subtraction techniques. This paper provides a basic methodology to convert a mono audio signal into stereo audio signal using behavioral approach in MATLAB. After that we have implemented hardware-in-the loop verification approach of the algorithm on Virtex-ml506 Board. We have used onboard audio Codec AC’97 for analog to digital conversion. Moreover we have added an extra facility of converting the sampling frequency from 8KHz to even 96KHz to enhance the audio quality. The present of System Generator in Simulink software is to generate the VHDL codes in order to produce a bit file that can be uploaded to Xilinx Vertex-ml506 FPGA board and finally the audio wave file is played using headphones.

Type : Research paper

Published : Volume-1,Issue-3


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-160   View Here

Copyright: © Institute of Research and Journals

| PDF |
Viewed - 43
| Published on 2014-01-20
   
   
IRAJ Other Journals
IJEEDC updates
Volume-10,Issue-6(June,2022) Want to join us ? CLick here http://ijeedc.iraj.in/join_editorial_board.php
The Conference World

JOURNAL SUPPORTED BY

ADDRESS

Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740