Paper Title :Design Of A Current Starved Ring Oscillator For Phase Locked Loop (PLL)
Author :Zainab Kazemi, Sajjad Shalikar, A. M. Buhari, Seyed Abbas Mousavi Maleki
Article Citation :Zainab Kazemi ,Sajjad Shalikar ,A. M. Buhari ,Seyed Abbas Mousavi Maleki ,
(2015 ) " Design Of A Current Starved Ring Oscillator For Phase Locked Loop (PLL) " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 34-39,
Volume-3, Issue-1
Abstract : This paper presents a five and three stages current starved Voltage Controlled Oscillator (CMOS VCO) for low
power Phase Lock Loop (PLL). The implemented design used a standard 0.18µm CMOS Technology with simulation CAD
software mentor graphics tool. uses two models of P-channel and N-channel Mosfets Model I and II. The Model I and II of
P-channel. The experimental results presentented suggests that the designed exibits twoVCO frequency ranging from
21MHz to 315.34 MHz at low power. The designed circuit is simulated using 180nm SCN018 Technology, and the product
of this current and voltage approximate the power consumption to be 105.3mW, the procedures of the system design are
illustrated step by step in this paper. The proposed design is suitable for PLL as a frequency multiplier based on its features
as presented.
Type : Research paper
Published : Volume-3, Issue-1
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-1612
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Copyright: © Institute of Research and Journals
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Published on 2015-01-05 |
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