International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Apr. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 133
Paper Published : 1712
No. of Authors : 4737
  Journal Paper


Paper Title :
Code-Driven Boundary Scan Testing

Author :Salim A. Jayousi, Mohd Saufee Muhammad

Article Citation :Salim A. Jayousi ,Mohd Saufee Muhammad , (2015 ) " Code-Driven Boundary Scan Testing " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 40-43, Volume-3, Issue-1

Abstract : During the last few years, integrated circuits (ICs) manufacturing was developed to be more compatible with “Design for Testability (DFT)” features. New embedded circuits were interpolated inside IC wafers. Such new additions increased the IC design complexity and as a result, the manufacturing overheads also increased. In this paper we introduce a new technique for testing onboard ICs with less embedded circuitry inside chips. The new technique depends basically on driving the test process by test code packets. The transmitted test packets have meaningful compartmentalized pieces of information which are capable to control all test activities. Test access port (TAP) is to be excluded from IC circuitry and shared over the board to serve all ICs together. TAP units activities are totally subjected to the data packet instructions. The design is simulated by NI Multisim software.

Type : Research paper

Published : Volume-3, Issue-1


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