International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Jun. 2023
Submitted Papers : 80
Accepted Papers : 10
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Issue Published : 123
Paper Published : 1646
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  Journal Paper

Paper Title :
Clock-Gating Strategy for Reducing Dynamic Power Dissipation on FPGA

Author :Jisha Varghese, Sreekala Ks

Article Citation :Jisha Varghese ,Sreekala Ks , (2019 ) " Clock-Gating Strategy for Reducing Dynamic Power Dissipation on FPGA " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 27-30, Volume-7,Issue-9

Abstract : In all silicon devices, power dissipation is one of the major problem which has to be eliminated. Reducing power minimizes the precise needs for cooling, improved durability, longer autonomy in battery operated devices and lower costs. Besides, power also has significant role in choice of the computing platform right at the outset. In case of field-programmable gate arrays (FPGAs), power dissipation is more as compared to equivalent application-specific integrated circuit (ASIC), but often compare favorably to conventional processors used for same functional tasks. Previous Clock-gating methods are not effective in implementation on FPGAs. This work presents a new Course Grained ON-OFF control method that can reduces power especially dynamic power by introducing a clock gating strategy. This work can introduce a technique that aims to achieve power savings by selectively switching off the circuit part when they are not temporarily active by using a Clock enabling circuit. This technique can be adopted for any application and can finally be integrated into the synthesis stage of design flow. Keywords - Clock-Gating, Dataflow, Clock Enabling Circuit

Type : Research paper

Published : Volume-7,Issue-9


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