International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Dec. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 116
Paper Published : 1605
No. of Authors : 4403
  Journal Paper


Paper Title :
Securing Data Transmission with Efficient Hardware Implementation of the AES`

Author :Komlan D. Assigbi, Jitendra K. Das

Article Citation :Komlan D. Assigbi ,Jitendra K. Das , (2019 ) " Securing Data Transmission with Efficient Hardware Implementation of the AES` " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 11-16, Volume-7,Issue-12

Abstract : We present in this paper an optimized hardware implementation of the Advanced Encryption Standard (AES). The overall optimization of this algorithm was achieved through a deep study and careful logic optimization at various architectural levels, and also keeping in mind design trade-offs. By making use of the tower field in the SBox and using direct computation in some other blocks of the circuit, we arrived at a topology having balanced hardware parameters, and can be used as a basis to develop more complex AES based encryption systems. A low area utilization was achieved and the power utilization was 323mW for a throughput of 506Mbps. The implementation was done on the Xilinx Artix 7 Basys 3 XC7A35T-1CPG236C FPGA after completing the design flow in Xilinx Vivado Design Suite 2018.2. Keywords - FPGA, Verilog HDL, Advance Encryption Standard (AES).

Type : Research paper

Published : Volume-7,Issue-12


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