Paper Title :Design and Evaluation of Vedic Multiplier using Various Types of Adder Topologies

Author :Ullas M S, Kiranmayi G R

Article Citation :Ullas M S ,Kiranmayi G R , (2021 ) " Design and Evaluation of Vedic Multiplier using Various Types of Adder Topologies " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 28-31, Volume-9,Issue-7

Abstract : Abstract - Vedic mathematics is a branch of ancient Indian mathematics. Multiplication is one of the basic operations in vedic mathematics. The technique of multiplying two numbers is defined with 16 sutras, Urdhvatiryagbhyam is one of them. Using this technique the multiplication will be faster when compared to traditional technique. Traditional method lags behind by using logical shifts operation which can be overridden by vedic multiplier. Hence vedic multiplication technique becomes faster. Design of vedic multiplier consists of AND logic and adders, hence the efficiency of adders will be a key role for overall performance.In this paper the design of 8 bit vedic multiplier using various types of adder topologies is explained. The design of carry look ahead adder, carry skip adder, carry save adder and ripple carry addertopologies are considered. The vedic multiplier using different types of adder aresimulated and synthesized. The performance evaluation of adders for vedic multiplication is done. The vedic multiplier using carry save adder is giving better performancewith respect to power consumption, area consumption, total gate count, total slack delay. Keywords - Carry Look Ahead Adder, Carry Skip Adder, Carry Save Adder and Ripple Carry Adder, Vedic Multiplier, Alu-Arithmetic Logic Unit.

Type : Research paper

Published : Volume-9,Issue-7

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