Paper Title :Low Complexity Reconfigurable Architecture for Direct Digital Frequency Synthesis

Author :Ponnana Ramprasad, Ashok Agarwal

Article Citation :Ponnana Ramprasad ,Ashok Agarwal , (2021 ) " Low Complexity Reconfigurable Architecture for Direct Digital Frequency Synthesis " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 1-4, Volume-9,Issue-6

Abstract : Abstract - With the tremendous growth in the demand for Wireless communication systems, the radio communication standards do change at a faster pace. Due to this, the hardware radio communications becomes obsolete. Software programmable or reconfigurable architecture for the implementation of radio communication system offers an efficient and cost effective solution to overcome this problem. It involves design of reconfigurable digital frequency synthesizers so that the specifications of required radio standard can be met. In this paper we propose to design reconfigurable Direct Digital Synthesizer (DDS) with reduced hardware complexity and minimum reconfiguration overhead to generate various carrier frequencies as required by the radio standard into consideration. The proposed design is implemented on various Field Programmable Gate Arrays (FPGAs) using Xilinx Vivado Design Suite and compared. It is observed that the proposed architecture not only switches the output frequencies at a faster rate with minimum overhead but also provides high frequency resolutionwhen compared with the existing DDS architectures. Keywords - DDS, Software Defined Radio, CORDIC, VHDL, FPGA

Type : Research paper

Published : Volume-9,Issue-6

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