International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Jan. 2019
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 70
Paper Published : 1196
No. of Authors : 3206
  Journal Paper

Paper Title
Novel High Speed Vedic Multiplier Using Compressors And Pipelining

Abstract
The multiplier and accumulator unit (MAC) is one of the integral units of ALU. With technological advancement in VLSI and communication fields, the demand for high speed processing and low area design grows. The high speed multiplier architecture is therefore necessary. Vedic mathematics is an ancient Indian mathematics technique discovered in early twentieth century. In this paper, a novel high speed 4-bit Vedic multiplier is proposed which can be extentened upto 32bit. The design uses most efficient Urdhwa Tiryagbhyam method of Vedic multiplication. The novel high speed 4:2 compressor based method of multiplication is used. Further improvement in speed can be done using pipelined architecture. Thus the hybrid approach of combing the compressor based Vedic multiplication with Pipelined architecture is proposed in this paper. Keywords- 4:2 compressor, Pipelined architecture, Urdhwa Tiryagbhyam sutra, Vedic multiplier.


Author - Amruta Ingle, Shruti Oza

Indexed - Google Scholar


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