International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Mar. 2019
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 72
Paper Published : 1212
No. of Authors : 3255
  Journal Paper

Paper Title
Implementation Of Parallel CRC Generation For High Speed Application

Abstract
In data communication there is technology named as “data transmission”. So in data transmission cyclic redundancy check (CRC) is very needful method for detecting transmission error. By the help of recursive formula in serial CRC, it is possible to find out the parallel CRC architecture. A Serial CRC calculation cannot initiate a high throughput while parallel CRC calculation can increase the throughput of CRC computations. Proposed CRC algorithm is designed for 32-bit which can be simulated on Xilinx tools using VHDL language. Its hardware implementation is possible on FPGA board of Spartan 6 families. The design is done with the help of encoder and decoder for the serial data transmission and reception of CRC. Keywords— CRC, VHDL, Xilinx


Author - Kiran U. Mane, Pr.R.M.Khaire

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