Paper Title :Design of 5 to 3 Compressor for High Speed Energy Efficient Arithmetic Circuits

Author :Snekha. S, Naveenaasre. S, Guru Prasath. K, K. Saranya

Article Citation :Snekha. S ,Naveenaasre. S ,Guru Prasath. K ,K. Saranya , (2022 ) " Design of 5 to 3 Compressor for High Speed Energy Efficient Arithmetic Circuits " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 15-18, Volume-10,Issue-6

Abstract : Abstract - Adders and Multipliers in arithmetic circuits have been considered a major circuit element to improve performance. In this paper, a new 5 to 3 compressor architecture based on input reordering is proposed. As a result of input reordering, the number of output combinations can be reduced to 13 from 32 and the circuit complexity reduces. It is employed in the partial product reduction stage of the 8-bit multiplier to showcase its efficiency. The proposed architecture is compared with the best existing designs presented in the state-of-the-art literature in terms of power, delay and area, area delay product, and energy parameters. Keywords - Delay, ALU, Input Re-ordering, Compressor, Multiplier.

Type : Research paper

Published : Volume-10,Issue-6

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