Paper Title :Implementation Of 24T Memristor Based Adder Architecture With Improved Performance

Author :Joy Chowdhury, j. K. Das, N. K. Rout

Article Citation :Joy Chowdhury ,j. K. Das ,N. K. Rout , (2015 ) " Implementation Of 24T Memristor Based Adder Architecture With Improved Performance " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 91-94, Volume-3, Issue-6

Abstract : In the recent history of electronics industry nano scale devices took a major leap through the invention of the physical memristor device in 2008 by Hewlett Packard Labs. These are considered to be novel devices finding extensive applications in the field of semiconductor memory integration and development. Design of logic function blocks are also an important application of these memristive devices due to its minimized area, power consumption and compatibility with existing CMOS fabrication technology. There are various design styles for designing digital logic such as MRL, IMPLY, MAGIC. In this paper a full adder which is the most basic digital design unit has been developed using MRL (Memristor Ratioed Logic) design style and then it was modified using the concept of mirror adder design thus obtaining further optimized values of delay and power. Keywords - Full adder, Memristor, MRL logic family, Optimization, digital logic, linear ion drift model.

Type : Research paper

Published : Volume-3, Issue-6

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