International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Statistics report
Aug. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 89
Paper Published : 1423
No. of Authors : 3841
  Journal Paper

Paper Title
Improved Analytical Modeling For Junctionless Transistor

In this paper, we have derived and proposed an analytical model of junctionless transistor by solving poisson equation with variable separation method. The 2-D poisson equation in both silicon and oxide regions are solved to deduce expressions of surface potential, threshold voltage and drain induced barrier lowering of double gate junctionless transistor. Behavior of Derived expression is compare with analytical model of junctionless DG-MOSFET and TCAD sentaurus results. Proposed results give good agreement with these results. Index Terms- Junctionless transistor, 2-D poisson equation, surface potential, Short channel effect (SCE), Drain Induced Barrier Lowering (DIBL).

Author - Vikkee, Ashutosh Nandi
DOI - 10.18479/ijeedc/2015/v3i7/48259

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| Published on 2015-07-04
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