International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 89
Paper Published : 1423
No. of Authors : 3841
  Journal Paper

Paper Title
Fpga Implementation Of Efficient Correlator For Ofdm Synchronization

Abstract
Orthogonal frequency division multiplexing (OFDM) is a viable technology for high-speed data transmission by virtue of its spectral efficiency and robustness to multi-path fading. These advantages can be achieved only with good synchronization both in time and frequency. The existing system consist of pipeline structure of correlator using DSP48E1 slices but it optimize a large amount of area and also it forms a delay so for reducing this problems we proposed a new model. The proposed model is designed using a custom designed hardware instead of DSP slices. So this reduces area optimization, delay formation, power consumption and also it can be used in any FPGA architecture. Index terms – Correlator, Field programmable gate arrays (FPGA), IEEE 802.16 standards, Orthogonal frequency division multiplexing (OFDM).


Author - Trishali S. Hiwarkar, sunil R. Gupta
DOI - 10.18479/ijeedc/2015/v3i7/48260

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| Published on 2015-07-04
   
   
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