International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 89
Paper Published : 1423
No. of Authors : 3841
  Journal Paper

Paper Title
Design Of A Large Signal Memory Array For High Frequency Microprocessors

Abstract
This paper focuses on designing an 80 bit 160 entry Register File for uncore applications like Cache controller, DRAM controller, Hard disk controller and Integrated graphics controller rather than the core instructions or data. The main objective is to develop a methodology to optimize the LSA in area, performance, power, robust to noise and be able to perform in low voltage conditions. This is done by determining the characterization results of Read and Write word line drivers and Bit line drivers. The characterization results are obtained using Cadence RTL Compiler . Keywords – Bit line driver, Memory cell, Register File, Word line driver.


Author - Ruchika Mishra, Rajendra Prasad
DOI - 10.18479/ijeedc/2015/v3i7/48262

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| Published on 2015-07-04
   
   
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