International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
May. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 111
Paper Published : 1546
No. of Authors : 4203
  Journal Paper


Paper Title :
Design Of A Large Signal Memory Array For High Frequency Microprocessors

Author :Ruchika Mishra, Rajendra Prasad

Article Citation :Ruchika Mishra ,Rajendra Prasad , (2015 ) " Design Of A Large Signal Memory Array For High Frequency Microprocessors " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 53-56, Volume-3, Issue-7

Abstract : This paper focuses on designing an 80 bit 160 entry Register File for uncore applications like Cache controller, DRAM controller, Hard disk controller and Integrated graphics controller rather than the core instructions or data. The main objective is to develop a methodology to optimize the LSA in area, performance, power, robust to noise and be able to perform in low voltage conditions. This is done by determining the characterization results of Read and Write word line drivers and Bit line drivers. The characterization results are obtained using Cadence RTL Compiler . Keywords – Bit line driver, Memory cell, Register File, Word line driver.

Type : Research paper

Published : Volume-3, Issue-7


DOI - 10.18479/ijeedc/2015/v3i7/48262

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