International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Statistics report
Jan. 2021
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 93
Paper Published : 1465
No. of Authors : 3971
  Journal Paper

Paper Title
High Speed Low Power Asic Design Of Multiplier Using Vedic Mathematics

the performance of any processor will mainly depend upon its power and delay. The power and delay should be less in order to get a high performance .Multipliers are the basic building blocks in almost all processors. Hence, there is a need for highly efficient and sophisticated multiplier. The need of efficient multiplier is to increase the processing speed of the system in real time signal and processing applications. A high speed low power multiplier design (ASIC) using Urdhva and Nikhilam sutra ofVedic mathematics is presented in this paper. The proposed urdhva and nikilam multipliers achieve 60%, 77% improvement in speed and 37%, 50% improvement in power respectively, as compared with that of conventional array multipliers. Keywords: Vedicmultiplier; Arraymultiplier; Urdhva;Nikhilam

Author - Navyashree Hosamane, G.Jyothi, M Z Kurian
DOI - 10.18479/ijeedc/2015/v3i7/48268

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| Published on 2015-07-04
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