International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
.
current issue
Volume-8,Issue-5  ( May, 2020 )
ARCHIVES
  1. Volume-8,Issue-4  ( Apr, 2020 )
  2. Volume-8,Issue-3  ( Mar, 2020 )
  3. Volume-8,Issue-2  ( Feb, 2020 )

Statistics report
Aug. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 89
Paper Published : 1423
No. of Authors : 3841
  Journal Paper

Paper Title
High Speed Low Power Asic Design Of Multiplier Using Vedic Mathematics

Abstract
the performance of any processor will mainly depend upon its power and delay. The power and delay should be less in order to get a high performance .Multipliers are the basic building blocks in almost all processors. Hence, there is a need for highly efficient and sophisticated multiplier. The need of efficient multiplier is to increase the processing speed of the system in real time signal and processing applications. A high speed low power multiplier design (ASIC) using Urdhva and Nikhilam sutra ofVedic mathematics is presented in this paper. The proposed urdhva and nikilam multipliers achieve 60%, 77% improvement in speed and 37%, 50% improvement in power respectively, as compared with that of conventional array multipliers. Keywords: Vedicmultiplier; Arraymultiplier; Urdhva;Nikhilam


Author - Navyashree Hosamane, G.Jyothi, M Z Kurian
DOI - 10.18479/ijeedc/2015/v3i7/48268

| PDF |
Viewed - 98
| Published on 2015-07-04
   
   
IRAJ Other Journals
IJEEDC updates
Volume-8,Issue-1(Jan,2020) Want to join us ? CLick here http://ijeedc.iraj.in/join_editorial_board.php
The Conference World

JOURNAL SUPPORTED BY

ADDRESS

Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740