International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
Follow Us On :
current issue
Volume-10,Issue-6  ( Jun, 2022 )
  1. Volume-10,Issue-5  ( May, 2022 )
  2. Volume-10,Issue-4  ( Apr, 2022 )
  3. Volume-10,Issue-3  ( Mar, 2022 )

Statistics report
Aug. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 114
Paper Published : 1562
No. of Authors : 4260
  Journal Paper

Paper Title :
Recent Developments In VBMC: A Formal Verification Tool For HDL Designs

Author :Asha Devi, Ajith K John, R. Dhanabal

Article Citation :Asha Devi ,Ajith K John ,R. Dhanabal , (2016 ) " Recent Developments In VBMC: A Formal Verification Tool For HDL Designs " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 32-35, Volume-4,Issue-6

Abstract : Verification is inevitable in order to make hardware designs reliable and bug free. The conventional method for hardware design verification involves simulation and testing. However, exhaustive testing and simulation over the entire behavior space of the design is infeasible even for designs of moderate size and complexity. Formal verification provides a feasible alternative for verification of hardware designs. Given a hardware design and functional property, a formal verification tool either proves that the design satisfies the property or generates an execution of the design violating the property. Application of such tools is highly recommended in hardware designs used in safety critical applications such as nuclear reactors. VHDL Bounded Model Checker (VBMC) is a formal verification tool for VHDL designs developed in-house at BARC. VBMC accepts a VHDL design, a functional property, and verification bound (number of cycles of operation) as inputs. It either reports that the design satisfies the functional property for the given verification bound or generates a counterexample providing the reason of violation. In case of satisfaction, the proof holds good for the verification bound. This paper presents the overview of the tool VBMC with focus on its recent developments. Keywords- Preprocessor, Property Translator, VHDL,VBMC

Type : Research paper

Published : Volume-4,Issue-6


Copyright: © Institute of Research and Journals

| PDF |
Viewed - 87
| Published on 2016-07-02
IRAJ Other Journals
IJEEDC updates
Volume-10,Issue-6(June,2022) Want to join us ? CLick here
The Conference World



Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740