International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Dec. 2022
Submitted Papers : 80
Accepted Papers : 10
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Acc. Perc : 12%
Issue Published : 116
Paper Published : 1605
No. of Authors : 4403
  Journal Paper


Paper Title :
Signal Integrity Fault Modeling And Filtering In Ultra-High-Speed SOCS For Long Interconnection

Author :Divyansh Jain, Vibha Dhurve, Akanksha Dixit

Article Citation :Divyansh Jain ,Vibha Dhurve ,Akanksha Dixit , (2016 ) " Signal Integrity Fault Modeling And Filtering In Ultra-High-Speed SOCS For Long Interconnection " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 50-52, Volume-4,Issue-7

Abstract : As feature sizes shrink and clock frequencies increase for high-performance system-on-a-chip (SOC) designs, signal integrity (SI), that is, the ability of an input signal to generate correct responses in a circuit is becoming a major concern for the interconnects between embedded cores As we approach 180nm technology the interconnect issues are becoming one of the main concerns in the testing of GHZ system on chip. This is achieved by considering the effect of inputs and parasitic RLC element of the inter connect. Voltage distortion (noise) and delay violation (skew) contribute to the signal integrity loss, ultimate functional error and reliability problems. Use the BIST-based test methodology to detect it. Keywords- VLSI- Very Large Scale Integration, BIST Methodology, SI , system-on-chip, interconnect testing Region and Signal Victim.

Type : Research paper

Published : Volume-4,Issue-7


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