International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 113
Paper Published : 1559
No. of Authors : 4245
  Journal Paper


Paper Title :
10 Bit 500 MHZ Current Steering DAC

Author :Sreemol S S

Article Citation :Sreemol S S , (2016 ) " 10 Bit 500 MHZ Current Steering DAC " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 39-42, Volume-4,Issue-8

Abstract : In this paper 10bit, 500M segmented current steering Digital to Analog converter is designed. The DAC is implemented using 90nm technology with a supply voltage of 1.2V.The design is implemented with the matching network, required for the current sources. Segmented architecture of the DAC is used in order to decrease the glitch and to improve the Monotoncity, even though that increases the cost. The spurious free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) performance of the segmented DAC architecture is also analyzed in this paper. Index Terms- Segmented architecture, Monotoncity, Spurious free dynamic range (SFDR), Signal to noise ratio (SNDR)

Type : Research paper

Published : Volume-4,Issue-8


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