Paper Title :Study Of High Performance Amba Ahb Reconfigurable Arbiter For On-Chip Bus Architecture

Author :Pravin S. Shete, Shruti Oza

Article Citation :Pravin S. Shete ,Shruti Oza , (2014 ) " Study Of High Performance Amba Ahb Reconfigurable Arbiter For On-Chip Bus Architecture " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 11-15, Volume-2,Issue-3

Abstract : Abstract- This paper focuses on study of Reconfigurable arbiter that can interface with any common IP core of a system, using specification of AMBA bus protocol. The arbiter plays a very important role to manage the resource sharing on the SOC platform. The scheme involves the typical AMBA features of single clock edge transition, Split transaction, several bus masters, burst transfer . The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers. The reconfigurable arbitration algorithm, such as highest priority or fair access and round robin can be implemented depending on the application requirements.

Type : Research paper

Published : Volume-2,Issue-3

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