International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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May. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 111
Paper Published : 1546
No. of Authors : 4203
  Journal Paper


Paper Title :
Design of Pulse Triggered Transmission Gate Based Power Efficient Flip Flop

Author :Preeti Kumari, Aastha Sachdeva, Neetika Yadav

Article Citation :Preeti Kumari ,Aastha Sachdeva ,Neetika Yadav , (2017 ) " Design of Pulse Triggered Transmission Gate Based Power Efficient Flip Flop " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 6-8, Volume-5,Issue-2

Abstract : In this paper, a transmission gate based low power pulse triggered flip-flop design is conferred. In this configuration, the clock pulse is generated with two input AND gate circuitry for reducing the discharging path and reduce the circuit complexity. In the proposed design input to output driving path inverter is deleted and the feedback is removed along with pseudo NMOS and the transistor is substituted with transmission gate logic. The transmission gate driven by generated clock pulse is utilized to drive the flip flop output. As compared to the conventional pulse triggered flip-flop, the proposed pulse triggered flip-flop design features are best power, along with minimum number of transistors. This is designed and simulated in X-manager 4 with 3.5 V supply voltage and 350 Nanometer technology. Index terms- Transmission Gate, Power Delay Product.

Type : Research paper

Published : Volume-5,Issue-2


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-6962   View Here

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