International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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May. 2022
Submitted Papers : 80
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  Journal Paper


Paper Title :
A Novel Design of Power and Area Optimization For 4x4 Booth Multiplier Using 180nm Technology

Author :Sudhakar Alluri, B.Rajendra Naik, N.S.S.Reddy, Ravindra Kumar Niranjan

Article Citation :Sudhakar Alluri ,B.Rajendra Naik ,N.S.S.Reddy ,Ravindra Kumar Niranjan , (2017 ) " A Novel Design of Power and Area Optimization For 4x4 Booth Multiplier Using 180nm Technology " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 61-67, Volume-5,Issue-2

Abstract : In Very-large-scale integration (VLSI) application area, delay and power are the important factors for any digital circuits. This paper presents four bit 4x4 Booth Multiplier mapped in Cadence Encounter(R) RTL Compiler Version v14.20- s013_1. By efficiently mapping into cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 180 nm technology, 1.8V. Based on digital signal processing (DSP) architectures, the code for low power is generated using 4x4 Booth Multiplier. Key words- High-Level Synthesis, 4x4 Booth Multiplier, low power, low area, delay, DSP, VLSI.

Type : Research paper

Published : Volume-5,Issue-2


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-6993   View Here

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