International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
May. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 111
Paper Published : 1546
No. of Authors : 4203
  Journal Paper


Paper Title :
Implementation Of Adaptive Clock Gating Technique For Low Power Circuits: A Review

Author :Shreya Maolanker, Swapnil Borpe, Bhagyashree Kalmegh, Nikhil Parkhi, Saurabh Giratkar

Article Citation :Shreya Maolanker ,Swapnil Borpe ,Bhagyashree Kalmegh ,Nikhil Parkhi ,Saurabh Giratkar , (2014 ) " Implementation Of Adaptive Clock Gating Technique For Low Power Circuits: A Review " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 69-72, Volume-2,Issue-5

Abstract : Abstract: Clock pulses are responsible for over 50% of dynamic power consumption in a synchronous circuit. Clock Gating is being used for reduction of power consumption in low power circuits for quite a while now. Adaptive clock gating is most rigorous of them all. Since gating the clock signals involve additional circuitry there exists a tradeoff between the additional number of gates and the total power consumption of gated clock. In this paper we go through the details of adaptive clock gating technique and the parameters which are to be taken into account while deciding the gating circuitry.

Type : Research paper

Published : Volume-2,Issue-5


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