Paper Title :An FPGA Implementation Of Ieee - 754 Double Precision Floating Point Unit Using Verilog

Author :Chaitanya A. Kshirsagar, P.M. Palsodkar

Article Citation :Chaitanya A. Kshirsagar ,P.M. Palsodkar , (2014 ) " An FPGA Implementation Of Ieee - 754 Double Precision Floating Point Unit Using Verilog " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 1-3, Volume-2,Issue-6

Abstract : Abstract- Arithmetic circuits form an important class of circuits in digital systems. With the remarkable progress in the very large scale integration (VLSI) circuit technology, many complex circuits, unthinkable yesterday have become easily realizable today. Algorithms that seemed impossible to implement now have attractive implementation possibilities for the future. In this paper an arithmetic unit based on IEEE standard for floating point numbers has been implemented on FPGA Board. Here FPU follows IEEE double precision format. The arithmetic unit implemented has a 64-bit processing unit which allows various arithmetic operations such as, Addition, Subtraction, Multiplication and Division on floating point numbers. Each operation can be selected by a particular operation code. We see that the overhead for double precision is less than that for single precision. The unit comprises of rounding and exception unit as specified in format. The FPU design achieved the operating frequency of 107MHz.

Type : Research paper

Published : Volume-2,Issue-6

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